(1) Field of the Invention
The present invention relates generally to computer systems and, in particular to computer systems employing emulator overlay memory support.
(2) Description of the Related Art
Emulators add value to a corresponding computer system by 1) giving a system designer the ability to test computer components on a printed circuit board (e.g., baseboard or a computer card), and 2) giving an application programmer the ability to modify software in a Read Only Memory (ROM) based system without having to re-program the ROM for every software modification (i.e., providing overlay memory support). Overlay memory support is easily achievable when the microprocessor package technology is a pin grid array (PGA) type, which is illustrated in FIG. 1A (bottom view) and FIG. 1B (side view). The emulator is connected to the computer system via an emulator probe. One simply removes the PGA component from a socket, which is coupled to a target printed circuit board (PCB), and inserts the emulator probe into this socket. The emulator probe includes a special version of the microprocessor that is within the PGA component. This emulator microprocessor includes logic and special signals dedicated for use by the emulator in testing and debugging a target PCB.
In addition, the emulator selectively uses the emulator probe to sever the connection of a target memory to a processor on the target board. By breaking the connection between the target memory and the local processor, the emulator can monitor the instruction fetch (e.g., addresses) addresses and allow either the target memory to provide the necessary data or the emulator over memory to provide the data instructions and addresses for the local processor to execute. The emulator overlay memory allows the emulator to provide data to the processor, regardless of the actual data included in the target memory.
One of the disadvantages of the PGA package technology is the cost associated with the packaging. Since the PGA package technology uses ceramic materials for the package, PGA technology is more expensive than other technologies (e.g., using plastic for the packaging). Accordingly, although the PGA packaging technology may be employed to provide for a high pin count (i.e., it may be adapted to accommodate applications requiring a high number of signal pins), the high costs associated with using ceramic materials becomes prohibitively high, especially when the area of the package is large.
Many chip manufacturers have migrated to a plastic-based packaging technology (e.g., plastic quad flat pack (PQFP) package). Although the PQFP technology is much more cost effective than the PGA type packages, this plastic technology has its own disadvantages. One of the disadvantages of the PQFP package is that it offers a smaller number of signal pins than a similarly sized PGA package. As can be seen in FIG. 1C and FIG. 1E, the PQFP technology only provides signal pins along the perimeter of the package. Another disadvantage of the PQFP technology is that the pins in the package are fragile and can easily be broken. FIG. 1D illustrates a side view of a PQFP packaged chip. Furthermore, when one attempts to increase the number of signal pins, the space between the pins correspondingly decreases, thereby increasing the probability of two adjacent pins contacting and causing signal corruption.
As a result of the above-noted disadvantages of the PQFP technology, chip manufacturers who require a high pin count and desire a plastic package have turned to ball grid array technology. A ball grid array (BGA) package provides a high signal pin count while maintaining a lower cost because the BGA packages are made from a plastic material. Since a BGA package is connected directly to the target board via solder (see FIG. 1G), the solution for providing memory support for PGA type packages is inoperable for the BGA packages (i.e., one cannot simply remove the BGA package from the target board).
One proposed solution to the foregoing problem is to provide a two step process. First, a circuit designer designs a board around a PGA microprocessor package for product development. During this stage the prior art emulators are used for debugging the initial hardware and software applications. Second, once the hardware and software development is completed, the circuit designer re-manufactures the board using a plastic quad flat pack (PQFP) package for production.
Accordingly, during the production phase, the emulator is of no value and cannot be used to locate production problems on the board, once the PQFP packages are used because of the incompatibility of the two different packages (i.e., the signal pins are arranged differently). Another disadvantage is that the chip manufacture is required to re-design the product for every different processor package. Furthermore, the emulator cannot be used for production de-bugging when a target memory on a production board is not functioning. Also, additional circuitry is required to download code to the computer system to locate the failure in these cases.
Accordingly, it would be desirable to provide a method and apparatus for providing emulator overlay memory support for BGA microprocessor packages without the overhead and limitations of the prior art solutions.
Another problem with the prior art solution is that overlay memory support was not available to a processor package that included a memory controller (i.e., the memory controller is not integrated into the same BGA package). Thus, it would be desirable to provide a method and apparatus for providing emulator overlay memory support to a BGA package having both an integrated processor and memory controller. Other aspects of the invention are drawn to such an improved method and apparatus.